`timescale 1ns/1ns
`define clk_period 20
module rom_tb();

reg clk;
reg [7:0]addr;
wire [127:0]data; 

rom rom_instance0(
	.address(addr),
	.clock(clk),
	.q(data)
);

initial clk = 0;
always #10 clk = ~clk;

initial begin
	addr = 8'd0;
	
	#201
	repeat (100) begin
		addr = addr + 1;
		#40;
	end
	#200;
	$stop;
end
endmodule
